From the 90 nm CMOS integrated circuit technique, Strain Channel Engineering with the purpose of enhancing carrier mobility of channel plays an increasingly important role with continuous reduction of a feature size of a device. A plurality of uniaxial process induced stress technology are used in device manufacturing process, that is, compressive stress or tensile stress is introduced in the channel direction so as to enhance the carrier mobility of channel and to enhance performance of the device. For example, for 90 nm process node, compressive stress in a PMOS device is provided by using embedded SiGe (e-SiGe) source/drain or using a (100) crystal orientation substrate in combination with a tensile stress contact etch stop layer (tCESL); for 65 nm process node, the first generation source/drain stress memorization technique (SMT×1) is further adopted on the basis of the 90 nm process node, for example, a dual contact etch stop layer is used; for 45 nm process node, the second generation source/drain stress memorization technique (SMT×2) is used on the basis of the previous technique, for example, e-SiGe technique may be used in combination with a tCESL or a dual CESL, besides, Stress Proximity Technique (SPT) may be used, moreover, a (110)-plane substrate is adopted for PMOS and a (100)-plane substrate is adopted for NMOS; after 32 nm process node, the third generation source/drain stress memorization technique (SMT×3) is used, for example, embedded SiC source/drain is used on the basis of the previous techniques to enhance the tensile stress in a NMOS device.
Moreover, technology of introducing stress to a channel can be realized by controlling a material or a cross-section shape of a channel or spacer apart from changing the materials of the substrate or source/drain. One example is that a dual stress liner (DSL) technique can be adopted. Another example is that a tensile stress SiNx layer spacer can be adopted for a NMOS and a compressive stress spacer can be adopted for a PMOS. Still another example is that the cross-section of the embedded SiGe source/drain is manufactured as a Σ-shaped so as to improve the channel stress in PMOS.
However, the effect of these conventional stress technologies is weakened increasingly with the continuous reduction in the size of devices. For a NMOS, dislocation and offset between the thin film layers providing stress become increasingly obvious with the reduction in the feature size, which requires providing higher stress precisely while the thickness of the thin films has to be thinned. For a PMOS, carrier mobility of channel in embedded SiGe source/drain technology significantly depends on the feature size, and thereby reduction in size compromises the effect of enhancing carrier mobility greatly.
A new idea is to provide a strain to the device channel by a metal gate stress (MGS), to thereby weaken the disadvantageous effect where conventional stress sources such as a source and drain heteroepitaxial layer and a stained inner liner insulating layer are continuously reduced with reduction in the device size, such that the stress layer can directly act on the channel, while independent of the size. For example, Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate/High-k Dielectric SOI FinFETs, published by ChangYongKang et al. on IEEE ELETRON DEVICE LETTERS, VOL. 29, NO. 5 on May, 2008, discloses that high-stressed TiN is used in the metal gate stack to apply a stress to the channel in the substrate directly, to thereby enhance the channel carrier mobility correspondingly and improve the device electrical performance. Besides, US patents NO. US2008/0203485A1 and US2004/0137703A1 also disclose similar structures.
On the other hand, starting from the 45 nm CMOS integrated circuit technology, with continuous reduction in the device feature size, the equivalent oxide thickness (EOT) of a gate insulating dielectric layer in a CMOS device must be reduced synchronously to suppress the short channel effect. However, the ultra-thin (e.g., 10 nm) conventional oxide layer or oxynitride layer may result in severe gate current leakage since the (relative) dielectric constant is not high (e.g., about 3.9) and the insulating capability can hardly endure the relatively high field strength in such an ultra-small device. Hence, a conventional polysilicon/SiON system is no longer applicable.
In view of this, high-K (HK) dielectric materials are started to be used to manufacture a gate insulating dielectric layer in the industry. However, the interfacial charges and polarization charges of high-K materials will cause difficulty in regulating the threshold of a device, and the combination of polysilicon and high-K materials will produce a Fermi-level pinning effect, thus such combination of polysilicon and high-K materials can not be used for regulating the threshold of a MOSFET, accordingly, the gate electrode shall employ different metal materials to regulate the threshold of a device, that is, using a metal gate (MG)/HK structure.
Metal electrodes of different work functions are needed for regulating the threshold of different MOSFETs, e.g., a NMOS and a PMOS. The regulation method using a single metal gate material may be adopted, but the range of regulation is limited. In an example of a planar SOI multi-gate device with lower standby power employing a single metal gate material, to correspond to a work function of 4.1 eV of n+ polysilicon and a work function of 5.2 eV of p+ polysilicon, an appropriate metal electrode may be selected such that the work function of the gate can be in the vicinity of the median value of the two, e.g., to be 4.65 eV or 4.65±0.3 eV. However, the device threshold is hard to be effectively controlled by such a fine regulation within a small range. The optimal process is to adopt gate electrodes of different metal materials, for example, conduction-band metal is used for the NMOS and valence-band metal is used for the PMOS such that the gate work functions of the NMOS and the PMOS can be located at the edges of the conduction band and the valence band, respectively, e.g., 4.1±0.1 eV and 5.2±0.1 eV, respectively. A detailed study of selection of the materials for these gate metal (including metal nitride) has been made in the industry, and no more unnecessary details will be provided here.
FIG. 1 illustrates a CMOSFET having a typical MG/HK structure under the manufacturing process of 45/32 nm by Intel Corporation, the left part is a PMOS, and the right part is a NMOS. Although the two parts are displayed to be adjacent to each other in the figure, they may have many intermediate separation elements in an actual layout, thus shall be specifically set depending on the design requirements in the layout, and likewise below. Particularly, the CMOS comprises a substrate 1, shallow trench isolations (STIs) 2, source and drain regions 3, source and drain extension regions 4, gate spacers 5, metal silicide layers 6 on the source and drain regions, a contact etch stop layer (CESL) 7, an interlayer dielectric layer (ILD) 8, gate insulating layers 9, gate conductive layers 10, and source and drain contacts 11. Wherein the source and drain regions 3 are preferably embedded stressed source and drain regions, for example, (raised) SiGe for a PMOS, and Si:C for a NMOS. The gate insulating layers 9 preferably comprise a multi-layer stack structure, for example, low-K (LK) interface layers such as SiO2 and high-K (HK) insulating dielectric layers such as Hf based oxide (for example, HfO2 etc.), wherein the interface layers are used to optimize the interfaces between the gate insulating layers and the channels in the the substrate to reduce the defects.
The gate conductive layers 10 preferably comprise a multi-layer stack structure, for example, a gate material layer 10a made from TiN for regulating a work function, a gate blocking layer 10b made from TaN etc. for selectively controlling gate filling, and a gate filling layer 10c made from TiAl etc. Wherein the gate conductive layer 10 of the PMOS comprises the above 10a, 10b and 10c, while the gate conductive layer 10 of the NMOS only comprises 10a and 10c, and in the NMOS, Al is diffused into the TiN layer to thereby form an TiAl/TiN—Al laminated structure. The CMOS device adjusts the depth of Al atoms in the TiAl layer being diffused into the TiN layer by a thickness ratio between the layer 10a and layer 10c, to thereby regulate the work function. Al being diffused into the HK insulating dielectric layer or being away from the HK insulating dielectric layer (equivalent to pure TiN metal gate) will both result in the work function to be increased and to be adaptive to a PMOS, while only Al being located at an upper part close to the HK insulating dielectric layer/TiN interface can result in a lower work function and be adaptive to a NMOS.
Specifically, the method for forming the multi-layer stack structure of the gate conductive layer 10 may comprise performing etching to form a PMOS gate trench and a NMOS gate trench, sequentially depositing a PMOS work function metal layer 10a and a NMOS work function metal diffusion blocking layer 10b in the two trenches, then performing selective etching to remove the NMOS work function metal diffusion blocking layer 10b from the NMOS gate trench, and depositing a filling metal 10c in the two trenches, wherein the filling metal 10c may also function as a NMOS work function diffusion metal layer, then performing CMP to expose the ILD 8. In such a way, MOSFET with a single layer HK dual work function metal gate can be formed.
However, the multi-layer gate stack structure of the gate conductive layer 10 does not have a higher stress, thus the channel carrier mobility can not be effectively enhanced and the device performance can not be greatly improved.